Conventional cache policies have been implemented in a number of different ways such as hard-coded as part of a design, adjustable via configuration pins and adjustable via memory protection or memory management units for tightly coupled caches. A tightly coupled cache is commonly directly connected to a central processor unit (CPU) and does not have a bus protocol implemented in a data path between the CPU and the cache. In the absence of a bus protocol, the cache policy to be used can be easily communicated to the cache controller as a direct output from a memory protection circuit or a memory management unit for the CPU.
If cache policies are hard-coded (i.e., fixed in the cache hardware), the cache policies can be too restrictive to be of use to a system programmer. Poor system performance or even incorrect operation can result from hard-coded policies. Configuration pins typically are used to define a limited set of options and are not normally used to define the cache policies by address region. Some existing processors define large blocks of fixed-size memory regions with a particular set of cache policies to be used for each block, but the granularity of the address regions or the cache policies are not always sufficiently flexible.